Weekly Report

Status update of Tavor-TD

1. RTL coding of Channel Estimation, approximately 30% done. (Bin)
2. Generate code coverage and function coverage report for Tx E-BIM. (Yun)
3. Study RM-HARQ design spec and write verification plan. (Yun)
4. Studying spec of channel estimation and matched filter. And begin to prepare test plan and test bench for channel estimation. (Chuntao)
5. Verifying Tx BIF with direct cases and random cases. Basically the functional verfication is almost done. (Gaohua, Weifeng)
6. Studying the LLD doc of JD Post processing. (Weifeng)
7. RTL coding of RM/HARQ. (Shengguo)
8. Work together with DSP team to setup FPGA environment. Debugging dsp’s spi driver, not closed yet. Coding spi’s wrap, and debugging using FPGA. (Shuo)

Plan for next week

1. Continue Tavor-TD RTL design, and deliver the 1st version source code for verification. (Bin)
2. Write testbench for HARQ and wait for random input definition for parameter C-model. (Yun)
3. Write basic reset and register test case for HARQ. (Yun)
4. Start testplan and testbench design for Channel Estimation. (Chuntao)
5. Close the Tx BIF verification with code and functional coverage reports. (Gaohua Weifeng)
6. Contine JD post processing LLD iterative discussion with Algr engineer and start micro-arch design. (Weifeng)
7. Deliver the 1st version source of HARQ for verification. (Shengguo)
8. Close SPI related issue and back to support codec related issues. (Shuo)

Weekly Report

Status update of Tavor-TD

1. Ongoing RTL coding of Channel Estimation. (Bin)
2. Delivered micro-architectural design spec of JD matched filter. (Bin)
3. RTL code review of JD blockv_gen. (Bin)
4. Completed Rx DCC & DAGC verification including code coverage report and analysis. (Chuntao, Weifeng)
5. Start studying Channel Estimation of verification. (Chuntao)
6. Ongoing verifying Tx BIF. (Gaohua, Weifeng)
7. Start studying post-JD processing module. (Weifeng)
8. Completed Tx E-BIM verification including code coverage report and analysis. (Yun, Shengguo)
9. Debug Turbo decoder's test cases and get more familiar with this design. (Shuo)
10. Dive into FIFO SPI module related issues. (Shuo)
11. Make design changes of ICS DLSync Code, especially fixing timing violations. (Lu)

Plan for next week

1. Continue RTL coding of Channel Estimation. (Bin)
2. Start RTL coding of JD matched filter after having it review with DSP and algr teams. (Bin)
3. RTL code review of Rx DCC & DAGC. (Bin)
4. Start to design testplan and testbench of Channel Estimation. (Chuntao)
5. Finish direct and random test cases of Tx BIF. (Gaohua, Weifeng)
6. Start post-JD micro-architectural design. (Weifeng)
7. Start studying HARQ/RM LLD spec for verification. (Yun)
8. Suport DSP team to develop TD transceiver SPI driver on Yarden platform. (Shuo)
9. Continue investigating Turbo decoder design. (Shuo)
10. Start study ICS Fast AGC LLD spec. (Lu)