Weekly Report

· Tuesday, June 17, 2008 · ,

Status update of Tavor-TD

1. RTL coding of Channel Estimation, approximately 30% done. (Bin)
2. Generate code coverage and function coverage report for Tx E-BIM. (Yun)
3. Study RM-HARQ design spec and write verification plan. (Yun)
4. Studying spec of channel estimation and matched filter. And begin to prepare test plan and test bench for channel estimation. (Chuntao)
5. Verifying Tx BIF with direct cases and random cases. Basically the functional verfication is almost done. (Gaohua, Weifeng)
6. Studying the LLD doc of JD Post processing. (Weifeng)
7. RTL coding of RM/HARQ. (Shengguo)
8. Work together with DSP team to setup FPGA environment. Debugging dsp’s spi driver, not closed yet. Coding spi’s wrap, and debugging using FPGA. (Shuo)

Plan for next week

1. Continue Tavor-TD RTL design, and deliver the 1st version source code for verification. (Bin)
2. Write testbench for HARQ and wait for random input definition for parameter C-model. (Yun)
3. Write basic reset and register test case for HARQ. (Yun)
4. Start testplan and testbench design for Channel Estimation. (Chuntao)
5. Close the Tx BIF verification with code and functional coverage reports. (Gaohua Weifeng)
6. Contine JD post processing LLD iterative discussion with Algr engineer and start micro-arch design. (Weifeng)
7. Deliver the 1st version source of HARQ for verification. (Shengguo)
8. Close SPI related issue and back to support codec related issues. (Shuo)

Weekly Report

· Monday, June 09, 2008 · ,

Status update of Tavor-TD
  1. Ongoing RTL coding of Channel Estimation. (Bin)
  2. Delivered micro-architectural design spec of JD matched filter. (Bin)
  3. RTL code review of JD blockv_gen. (Bin)
  4. Completed Rx DCC & DAGC verification including code coverage report and analysis. (Chuntao, Weifeng)
  5. Start studying Channel Estimation of verification. (Chuntao)
  6. Ongoing verifying Tx BIF. (Gaohua, Weifeng)
  7. Start studying post-JD processing module. (Weifeng)
  8. Completed Tx E-BIM verification including code coverage report and analysis. (Yun, Shengguo)
  9. Debug Turbo decoder's test cases and get more familiar with this design. (Shuo)
  10. Dive into FIFO SPI module related issues. (Shuo)
  11. Make design changes of ICS DLSync Code, especially fixing timing violations. (Lu)
Plan for next week
  1. Continue RTL coding of Channel Estimation. (Bin)
  2. Start RTL coding of JD matched filter after having it review with DSP and algr teams. (Bin)
  3. RTL code review of Rx DCC & DAGC. (Bin)
  4. Start to design testplan and testbench of Channel Estimation. (Chuntao)
  5. Finish direct and random test cases of Tx BIF. (Gaohua, Weifeng)
  6. Start post-JD micro-architectural design. (Weifeng)
  7. Start studying HARQ/RM LLD spec for verification. (Yun)
  8. Suport DSP team to develop TD transceiver SPI driver on Yarden platform. (Shuo)
  9. Continue investigating Turbo decoder design. (Shuo)
  10. Start study ICS Fast AGC LLD spec. (Lu)

Weekly Report 2008/5/31

· Saturday, May 31, 2008 · ,

Status update of Tavor-TD
  1. Delivered Channel Estimation micro-architectural design spec. (Bin)
  2. Review the JD matched filter LLD spec. (Bin)
  3. RTL code review on Rx DCC & DAGC and JD block-V gen. (Bin)
  4. Investigate the design detail of Turbo Codec IP and its test cases. (Shuo)
  5. Study algorithm of Turbo Codec. (Shuo)
  6. Passed all 7 testcase of Rx DCC & DAGC including direct test and random test. (Chuntao, Weifeng)
  7. Generated coverage report: Now the conditional coverage is 97.31% and toggle is 93.74%. Other 3 coverages are all 100%.(Chuntao)
  8. Start running the basic register test of Tx BIF module. (Weifeng)
  9. Debugging Tx EBIM and finished direct test. (Shengguo, Yun)
  10. Finished JD block-V generation verification including direct test and random test, as well as its verifiation coverage report. (Gaohua, Xikai)
  11. Get the comprehensive verification platform on Tx BIF done and start direct testcase development. (Gaohua)
  12. Debugging on ICS DLsync code correlation. (Lu)
  13. Setup the template on module-level verification platform, and setup the verification QA mechanism. (Xikai)
Next week's plan of Tavor-TD
  1. Have a joint review meeting with DSP group and Algr group on Channel Estimation micro-arch design. (Bin)
  2. Start Channel Estimation RTL coding. (Bin)
  3. Start JD match filter micro-arch design. (Bin)
  4. Focus on Turbo Decoder and try to figure out the reuse method of this IP. (Shuo)
  5. Help DSP team to setup the FPGA environment to accommodate the SPI driver development. (Shuo)
  6. Start Channel Estimation testplan and testbench design. (Chuntao)
  7. Continue on Rx DCC & DAGC coverage report analysis and get this module closed. (Chuntao, Weifeng)
  8. Continue on verification of Tx BIF. (Weifeng, Gaohua))
  9. Start Post-JD processing micro-architectural design. (Weifeng)
  10. Finish Tx EBIM random test. (Shengguo, Yun)
  11. Finish Tx RM/HARQ micro-arch design and deliver its design spec. (Shengguo)
  12. Add a minor change on JD block-V gen, and get it verified. (Gaohua)
  13. Continue work on ICS DLsync code correlation. (Lu)
  14. Start TDMA engine verifcation. (Xikai)

Weekly Report 2008/5/24

· Sunday, May 25, 2008 · ,

Status update of Tavor-TD
  1. Channel Estimation micro-architectural design and documentation. This task is 80% finished. (Bin)
  2. Ongoing JD LLD iteration with algorithm engineer. (Bin)
  3. Ported simulation environment from modelsim to vcs. (Shuo)
  4. Turbo encoder simulation is ok, still debugging decoder.Need more knowledge about modem and turbo codec itself. (Shuo)
  5. Completed RTL coding of the EBIM and start debugging. (Shengguo)
  6. Write rough RM/HARQ spec. (Shengguo)
  7. EBIM verification plan and test plan review . (Yun)
  8. Write EBIM testbench and write basic reset/register test case. (Yun)
  9. Finished DCC & DAGC testbench design and start verification. (Chuntao)
  10. Debugging RTL of DCC & DAGC. (Weifeng)
  11. Finished RTL revision of Tx BIF. (Weifeng)
  12. Completed RTL coding of Block-V Generation, and start debugging. (Gaohua)
  13. Modified the Tx BIF testbench according to the revised RTL design and C-model. (Gaohua)
  14. Deliver the RTL code of TDMA engine. (Lu)
Plan for next week
  1. Deliver Channel Estimation micro-arch design spec, and get it reviewed. (Bin)
  2. Start JD matched filter micro-architectural design. (Bin)
  3. Study turbo codec algorithm (Shuo)
  4. Trace the design and gain more information about turbo codec. (Shuo)
  5. Continue debugging EBIM. (Shengguo)
  6. Detail HARQ/RM structure. (Shengguo)
  7. Verify EBIM with random test cases. (Yun)
  8. Continue verifying DCC & DAGC. (Chuntao)
  9. Continue debugging RTL of DCC & DAGC. (Weifeng)
  10. Debug the revised RTL of Tx BIF. (Weifeng)
  11. Debug RTL of Block-V generation. (Gaohua)
  12. Debug RTL of Tx BIF. (Gaohua)
  13. Start verifcation effort of TDMA engine. (Lu)

Weekly Report 5/17/08

· Saturday, May 17, 2008 · ,

Status update of TD
  1. Micro-architectural design of Channel Estimation. (Bin)
  2. Completed RTL design of Rx buffer. (Bin)
  3. Designed Verilog template for DSP and HW accessing SRAM/RF sharing one memory port. (Bin)
  4. Ongoing JD matched filter LLD iteration with algr engineer. (Bin)
  5. Discussed with Qian Li(algorithm team) about tx BIF module C model interface and have confirmed a draft version. (Gaohua)
  6. Investigated the timeslot format types in protocol file(3GPPTS25.221) and thought about the randomize generation in my testbench. (Gaohua)
  7. Discussed with Ming Zheng about the BlockV LLD and confirmed some concern problems(shift number, walsh code, and so on) (Gaohua)
  8. Released a version of the BlockV registers files(in attachment) and finished BlockV RTL coding for Q=16 mode(check in cvs, named blcokv_gen) (Gaohua)
  9. Finished RTL coding of DCC & DAGC. (Weifeng)
  10. Updated the Tx BIF design spec and revised RTL design. (Weifeng)
  11. Finish the EBIM spec with some feedback and detailed internal structure. (Shengguo)
  12. Modify the design, interface, sub-module spliting, and .etc. (Shengguo)
  13. Descuss EBIM C-model design for verification. (Yun)
  14. Write EBIM verification plan and test plan . (Yun)
  15. Write the random stimulus generator for TXBIM.
  16. Completed the DCC & DAGC testplan. (Chuntao)
  17. Designing DCC & DAGC testbench, get 70~80% done. (Chuntao)
  18. RTL design of TDMA engine. (Lu)
Plan for next week
  1. Continue Channel Estimation micro-arch design and deliver its draft spec. (Bin)
  2. Continue JD LLD iteration with algr engineer. (Bin)
  3. To implement the slot format type randomize generation in BIF testbench. (Gaohua)
  4. Finish block-V generation RTL code and deliver it for verification. (Gaohua)
  5. Start DCC & DAGC verification. (Weifeng, Chuntao)
  6. Start Tx BIF verification. (Weifeng, Gaohua)
  7. Finish EBIM RTL coding, and run simulation for basic test vector. (Shengguo)
  8. Deliver a initial RM spec as final LLD. (Shengguo)
  9. Deliver EBIM testplan for review. (Yun)
  10. Design EBIM testbench. (Yun)
  11. Finish TDMA RTL coding and deliver it for verification. (Lu)

Weekly Report 2008/5/9

· Friday, May 09, 2008 · ,

Status update of TD
  1. Modify Tx BIF module and update the design spec per System group's change. (Weifeng)
  2. RTL coding of Rx DCC & DAGC module. Hope to be delivered early next week. (Weifeng)
  3. Re-evaluated the JD path, particularly for timing budget in WF mode. (Bin)
  4. Discussing the CYD module for VLSI implementation issues with algr engineers. (Bin)
  5. RTL designing Rx buffer. (Bin)
  6. Micro-architectural design of Channel Estimation. (Bin)
  7. Finish discussion and chang about EBIM structure and modify the spec. (Shengguo)
  8. RTL coding of E-DCH mode interleaver. (Shengguo)
  9. Preparing the RM/HARQ micro-arch spec. (Shengguo)
  10. Read Tx BIM HLD spec and discuss issues with System engineer. (Yun)
  11. Writing C model requirement and deliver it to corresponding algr engineer. (Yun)
  12. Update the random stimulus generator for Tx BIM. (Yun)
  13. Be assigned the verification task of Rx DCC & DAGC module. (Chuntao)
  14. Getting familar with Channel Estimation. (Chuntao)
  15. Get Tx BIF testplan reviewed within ASIC Team. (Gaohua)
  16. Designing Tx BIF testbench. (Gaohua)
  17. Investigate the Block-V Generation module for RTL implementation. (Gaohua)
  18. Setup debug env. for 8206 EVB board. So far data receiving via 10bit interface seems OK. (Shuo)
Plan for next week
  1. Get the Rx DCC & DAGC RTL coding done, and start functional verification. (Weifeng)
  2. Get the modification of Tx BIF done for both RTL and documentation, and start functional verification. (Weifeng)
  3. Have a review meeting on demodulation path with System and Algr groups. (Bin, Xikai, Weifeng)
  4. Have a review meeting on TDMA microarchitectural design. (Lu, Bin, Xikai)
  5. Review the Verilog Design Guide. (ASIC Team)
  6. Micro-architectural design of Channel Estimation and its documentation. (Bin)
  7. Finish Rx buffer design. (Bin)
  8. Design Verilog template for memory access from both functional block and ASPEC bus. (Bin)
  9. Continue JD LLD iteration with algr guys. (Bin)
  10. Discuss architecture of EBIM for 2816/5ms data with System engineers. (Shengguo)
  11. Study HARQ hardware structure. (Shengguo)
  12. Discuss with algr engineer about Tx BIM C model. (Yun)
  13. EBIM testplan documentation. (Yun)
  14. Deliver testplan of DCC & DAGC. (Chuntao)
  15. Start testbench design of DCC & DAGC. (Chuntao)
  16. Deliver testbench of Tx BIF and start verification. (Gaohua)
  17. Start RTL coding of Block-V Generation. (Gaohua)
  18. Finish 10bit interface testing and transfer to System Team for SPI driver debug and tune. (Shuo)

Weekly Report 2008/4/30

· Wednesday, April 30, 2008 · ,

Status update of TD-SCDMA
  1. Review the micro-arch design of Rx DCC & DAGC. (ASIC Team)
  2. Reviewed the micro-arch design of JD Block-V Generation. (ASIC Team)
  3. Reviewed the SystemVerilog platform for module-level verification. (ASIC Team)
  4. Reviewed the HLD specification of TDMA engine. (Xikai, Lu, Bin)
  5. Ongoing Tx EBIM HLD iterative procedure and micro-arch design. (Shengguo, Yun)
  6. Study HARQ spec. (Shengguo)
  7. Ongoing JD Channel Estimation LLD iterative procedure. (Bin)
  8. Ongoing JD Matched Filter/Correlation Matrix LLD iterative procedure. (Bin)
  9. Re-evaluate the time consumption of JD path. (Bin)
  10. Study SystemVerilog for verification. (Bin)
  11. Ongoing TDMA HLD iterative procedure. (Lu)
  12. Study Channel Estimation for verification. (Chuntao)
  13. Designing testplan and testbench of Tx BIF for verification. (Gaohua)
  14. Designing RTL of Rx DCC & DAGC. (Weifeng)
Plan for next week
  1. Have a review meeting on Tx BIF testplan. (ASIC Team)
  2. Start Tx BIF verification. (Gaohua)
  3. Start Block-V Generation RTL design. (Gaohua)
  4. Start micro-architectural design of TDMA engine. (Lu)
  5. Start micro-architectural design of Channel Estimation. (Bin)
  6. Start testplan and testbench design of DCC & DAGC. (Bin)
  7. Continue JD LLD iterative procedure with algr designer. (Bin)
  8. Re-evaluate the time consumption of JD path, especially for CYD/FS/BS. (Bin)
  9. Start to design the Rx buffer (E1 / MA / E2). (Bin)
  10. Continue studying Channel Estimation for verification. (Chuntao)
  11. Finish DCC & DAGC RTL design and have it delivered. (Weifeng)
  12. Continue Tx EBIM micro-architectural design. (Shengguo)
  13. Continue Tx EBIM testbench design. (Yun)

Weekly Report 2008/4/25

· Friday, April 25, 2008 · ,

Status update of TD-SCDMA
  1. Delivered micro-architectural design spec of JD Block-V Generation. (Xia Bin)
  2. Ongoing the iterative procedure on JD Matched Filter and Modify-module with algorithm designer. (Xia Bin)
  3. Delivered a guide for micro-arch documentation. (Xia Bin)
  4. Delivered micro-architectural design spec of Rx DCC & DAGC (Peng Weifeng)
  5. Ongoing testplan on Tx BIF. (Chen Gaohua)
  6. Delivered testbench overview of RRC Rx filter (Chen Gaohua)
  7. Ongoing the iterative procedure on Tx EBIM with L1 designers. (Hao Shengguo, Zhang Yun)
  8. Designing Tx EBIM micro-architecture (Hao Shengguo)
  9. Designing Tx EBIM testbench (Zhang Yun)
  10. Delivered testbench overview of FFT engine. (Zhang Yun)
  11. Reviewing the TDMA HLD draft spec (Shi Lu)
Plan for next week
  1. Have a review meeting on micro-arch design of DCC & DAGC. (ASIC Team)
  2. Have a review meeting on micro-arch design of JD Block-V Generation. (ASIC Team)
  3. Have a review meeting on HLD spec of TDMA engine with system group. (Shi Lu, Zhao Xikai, Xia Bin)
  4. Have a review meeting on Tx BIF testplan. (ASIC Team)
  5. Have a review meeting on Gaohua and Yun's verifcation platform. (ASIC Team)
  6. Start RTL design of Rx DCC & DAGC and complete the Alpha version. (Peng Weifeng)
  7. Deliver testplan documentation on Tx BIF for reviewing. (Chen Gaohua)
  8. Start RTL design of JD Block-V Generation if designer is available. (Chen Gaohua)
  9. Continue Tx EBIM micro-arch designing. (Hao Shengguo)
  10. Continue Tx EBIM testbench designing. (Zhang Yun)
  11. Go on micro-arch design of JD Channel Estimation and documentation. (Xia Bin)
  12. Go on iterative procedure on LLD of Joint Detection sub-modules with algr designers. (Xia Bin)
  13. Start iterative procedure on HLD of TDMA engine. (Shi Lu)