TD milestones for next week

· Sunday, May 25, 2008 · ,

Following milestones would be archieved by the next weekend (Friday, May 30, 2008)

L1 System Phase (Shiyi's team)
  1. Complete HSDPA HLD documentation.
  2. Complete Initial Cell Search Fast AGC LLD design.
Algorithm Phase (Stone's team)
  1. Deliver fixed-point C code of JD matched filter.
  2. Deliver fixed-point C code of HARQ.
ASIC Phase (Xikai's team)
  1. Complete Block-V generation RTL coding.
  2. Complete JD matched filter LLD iteration and joint review.
  3. Complete HARQ LLD iteration and joint review.
Preacted or Delayed Items
  1. Channel Estimation delayed 2 weeks at ASIC micro-architectural design stage.

TD milestones for next week

· Saturday, May 17, 2008 · ,

L1 System Phase (Shiyi's team)
  1. Finish HARQ(RM) interface design and deliver HSUPA LLD spec.
  2. Finish JD Matched Filter LLD design.
Algorithm Phase (Stone's team)
  1. Deliver JD Matched Filter LLD spec.
  2. Deliver HARQ LLD spec.
ASIC Phase (Xikai's team)
  1. Deliver Channel Estimation micro-arch design spec.
  2. Finish DCC & DAGC RTL verification.
  3. Complete Block-V Gen testplan and testbench.
  4. Finish EBIM RTL verifiction.
  5. Finish interfacing with RF daughter card. (already done)

Milestone List for Next Week

· Saturday, May 10, 2008 · ,

Following milestones would be achieved by the next weekend (Friday, May 16th, 2008)
  • L1 System Phase (Shiyi's Team)
  1. Finish IR buffer/HARQ HSDPA HLD design.
  • Algorithm Phase (Stone's Team)
  1. Finish C coding of Channel Estimation.
  2. Deliver Block-V Generation LLD spec.
  3. Deliver EBIM LLD spec.
  • ASIC Phase (Xikai's Team)
  1. Deliver micro-architectural design spec of Channel Estimation.
  2. Finish DCC & DAGC RTL coding.
  3. Deliver DCC & DAGC testplan for review.
  4. Finish DCC & DAGC testbench design for verification.

Milestone List for Next Week

· Wednesday, April 30, 2008 · ,

Following milestones would be achieved by the next weekend (Friday, May 9th, 2008)
  • L1 System Phase (Shiyi's Team)
  1. HSDPA HLD for BIM/EBIM interface design (Shiyi, Zhiliang)
  2. Measurement HLD (Shiyi, Michael)
  3. HSUPA LLD for BIM/EBIM interface design (Zhiliang)
  4. Block-V LLD interface design (Shiyi, Dengwei)
  • Algorithm Phase (Stone's Team)
  1. Channel Estimation fixed-point C code (Liang)
  2. DCC & DAGC fixed-point C code (Ming)
  3. EBIM LLD spec (NA)
  • ASIC Phase (Xikai's Team)
  1. Channel Estimation micro-architecture draft (Bin)
  2. DCC & DAGC testplan (Bin)
  3. DCC & DAGC RTL design (Weifeng)
  4. Tx BIF testplan (Gaohua)

Milestone List for Next Week

· Friday, April 25, 2008 · ,

Following milestones would be achieved by the next weekend (Friday, May 2nd, 2008)
  • L1 System Phase
  1. HSUPA BIM/EBIM interface design spec (Fu Zhiliang)
  2. HSUPA HARQ(RM) interface design spec (Fu Zhiliang)
  3. Channel Estimation LLD design document (Zhu Shiyi, Xiao Dengwei)
  • Algorithm Phase
  1. None
  • ASIC Phase
  1. Finalize DCC & DAGC micro-arch design spec (Peng Weifeng)
  2. Kick off TDMA micro-arch design (Shi Lu)
  3. Deliver test plan document of Tx BIF and have it reviewed with ASIC Team (Chen Gaohua)