Milestone List for Next Week

· Wednesday, April 30, 2008 · ,

Following milestones would be achieved by the next weekend (Friday, May 9th, 2008)
  • L1 System Phase (Shiyi's Team)
  1. HSDPA HLD for BIM/EBIM interface design (Shiyi, Zhiliang)
  2. Measurement HLD (Shiyi, Michael)
  3. HSUPA LLD for BIM/EBIM interface design (Zhiliang)
  4. Block-V LLD interface design (Shiyi, Dengwei)
  • Algorithm Phase (Stone's Team)
  1. Channel Estimation fixed-point C code (Liang)
  2. DCC & DAGC fixed-point C code (Ming)
  3. EBIM LLD spec (NA)
  • ASIC Phase (Xikai's Team)
  1. Channel Estimation micro-architecture draft (Bin)
  2. DCC & DAGC testplan (Bin)
  3. DCC & DAGC RTL design (Weifeng)
  4. Tx BIF testplan (Gaohua)

Weekly Report 2008/4/30

· Wednesday, April 30, 2008 · ,

Status update of TD-SCDMA
  1. Review the micro-arch design of Rx DCC & DAGC. (ASIC Team)
  2. Reviewed the micro-arch design of JD Block-V Generation. (ASIC Team)
  3. Reviewed the SystemVerilog platform for module-level verification. (ASIC Team)
  4. Reviewed the HLD specification of TDMA engine. (Xikai, Lu, Bin)
  5. Ongoing Tx EBIM HLD iterative procedure and micro-arch design. (Shengguo, Yun)
  6. Study HARQ spec. (Shengguo)
  7. Ongoing JD Channel Estimation LLD iterative procedure. (Bin)
  8. Ongoing JD Matched Filter/Correlation Matrix LLD iterative procedure. (Bin)
  9. Re-evaluate the time consumption of JD path. (Bin)
  10. Study SystemVerilog for verification. (Bin)
  11. Ongoing TDMA HLD iterative procedure. (Lu)
  12. Study Channel Estimation for verification. (Chuntao)
  13. Designing testplan and testbench of Tx BIF for verification. (Gaohua)
  14. Designing RTL of Rx DCC & DAGC. (Weifeng)
Plan for next week
  1. Have a review meeting on Tx BIF testplan. (ASIC Team)
  2. Start Tx BIF verification. (Gaohua)
  3. Start Block-V Generation RTL design. (Gaohua)
  4. Start micro-architectural design of TDMA engine. (Lu)
  5. Start micro-architectural design of Channel Estimation. (Bin)
  6. Start testplan and testbench design of DCC & DAGC. (Bin)
  7. Continue JD LLD iterative procedure with algr designer. (Bin)
  8. Re-evaluate the time consumption of JD path, especially for CYD/FS/BS. (Bin)
  9. Start to design the Rx buffer (E1 / MA / E2). (Bin)
  10. Continue studying Channel Estimation for verification. (Chuntao)
  11. Finish DCC & DAGC RTL design and have it delivered. (Weifeng)
  12. Continue Tx EBIM micro-architectural design. (Shengguo)
  13. Continue Tx EBIM testbench design. (Yun)

Meeting Minutes 2008/4/28

· Monday, April 28, 2008 ·

Attendees
  1. Zhao Xikai, Xia Bin, Peng Weifeng, Chen Gaohua, Zhu Shiyi, Yin Xiaojun, Xiao Dengwei, Liu Shi, Zheng Ming
Agenda
  1. DCC & DAGC micro-architectural design review
  2. JD Block-V Generation micro-architectural design review
Synopsis
  1. Midamble from RRC Filter stores in Rx MA buffer.
  2. Midamble from DCC & DAGC stores in FFT engine for immediately kick-off Channel Estimation.
  3. Add flags for MA buffer interface to indicate either original MA or DCCed MA.
  4. Apart from Channel Estimation, FFT engine should also be able to act as a standalone hardware accelerator for DSP.
  5. Add TDMA timestamps register for DSP read.
  6. Fix parameters Q=16, W=17 in JD Block-V Generation.
Action Items
  1. Update documentation of DCC & DAGC (Peng Weifeng)
  2. Update documentation of JD Block-V Generation (Xia Bin)
  3. Start DCC & DAGC RTL coding (Peng Weifeng)
  4. Start JD Block-V Generation RTL coding (Chen Gaohua)

Milestone List for Next Week

· Friday, April 25, 2008 · ,

Following milestones would be achieved by the next weekend (Friday, May 2nd, 2008)
  • L1 System Phase
  1. HSUPA BIM/EBIM interface design spec (Fu Zhiliang)
  2. HSUPA HARQ(RM) interface design spec (Fu Zhiliang)
  3. Channel Estimation LLD design document (Zhu Shiyi, Xiao Dengwei)
  • Algorithm Phase
  1. None
  • ASIC Phase
  1. Finalize DCC & DAGC micro-arch design spec (Peng Weifeng)
  2. Kick off TDMA micro-arch design (Shi Lu)
  3. Deliver test plan document of Tx BIF and have it reviewed with ASIC Team (Chen Gaohua)

Weekly Report 2008/4/25

· Friday, April 25, 2008 · ,

Status update of TD-SCDMA
  1. Delivered micro-architectural design spec of JD Block-V Generation. (Xia Bin)
  2. Ongoing the iterative procedure on JD Matched Filter and Modify-module with algorithm designer. (Xia Bin)
  3. Delivered a guide for micro-arch documentation. (Xia Bin)
  4. Delivered micro-architectural design spec of Rx DCC & DAGC (Peng Weifeng)
  5. Ongoing testplan on Tx BIF. (Chen Gaohua)
  6. Delivered testbench overview of RRC Rx filter (Chen Gaohua)
  7. Ongoing the iterative procedure on Tx EBIM with L1 designers. (Hao Shengguo, Zhang Yun)
  8. Designing Tx EBIM micro-architecture (Hao Shengguo)
  9. Designing Tx EBIM testbench (Zhang Yun)
  10. Delivered testbench overview of FFT engine. (Zhang Yun)
  11. Reviewing the TDMA HLD draft spec (Shi Lu)
Plan for next week
  1. Have a review meeting on micro-arch design of DCC & DAGC. (ASIC Team)
  2. Have a review meeting on micro-arch design of JD Block-V Generation. (ASIC Team)
  3. Have a review meeting on HLD spec of TDMA engine with system group. (Shi Lu, Zhao Xikai, Xia Bin)
  4. Have a review meeting on Tx BIF testplan. (ASIC Team)
  5. Have a review meeting on Gaohua and Yun's verifcation platform. (ASIC Team)
  6. Start RTL design of Rx DCC & DAGC and complete the Alpha version. (Peng Weifeng)
  7. Deliver testplan documentation on Tx BIF for reviewing. (Chen Gaohua)
  8. Start RTL design of JD Block-V Generation if designer is available. (Chen Gaohua)
  9. Continue Tx EBIM micro-arch designing. (Hao Shengguo)
  10. Continue Tx EBIM testbench designing. (Zhang Yun)
  11. Go on micro-arch design of JD Channel Estimation and documentation. (Xia Bin)
  12. Go on iterative procedure on LLD of Joint Detection sub-modules with algr designers. (Xia Bin)
  13. Start iterative procedure on HLD of TDMA engine. (Shi Lu)

HR Allocation

· Tuesday, April 22, 2008 ·

TD-SCDMA UE Chipset TDMA

  • Syzhu,xjyin Lu Shi Xikai Zhao
TD-SCDMA UE Chipset DC & DAGC
  • Syzhu Ming Weifeng Peng Bin Xia
TD-SCDMA UE Chipset Channel Estimation
  • Syzhu Liang Bin Xia Chuntao Chen
TD-SCDMA UE Chipset BlockV
  • Syzhu ,Dwxiao Ming Gaohua Chen Xikai Zhao
TD-SCDMA UE Chipset Match Filter
  • Syzhu ,Dwxiao Ming Bin Xia Chuntao Chen
TD-SCDMA UE Chipset Cholesky
  • Syzhu ,Dwxiao Ming Bin Xia Chuntao Chen
TD-SCDMA UE Chipset RG
  • Syzhu ,Dwxiao Ming Bin Xia Chuntao Chen
TD-SCDMA UE Chipset FS
  • Syzhu ,Dwxiao Ming/Liang Bin Xia Chuntao Chen
TD-SCDMA UE Chipset BS
  • Syzhu ,Dwxiao Liang Bin Xia Chuntao Chen
TD-SCDMA UE Chipset Post JD
  • Syzhu ,Dwxiao Liang Gaohua Chen Chuntao Chen
TD-SCDMA UE Chipset Scaling Before Decoder
  • Syzhu ,Dwxiao Liyun TBH Chuntao Chen
TD-SCDMA UE Chipset DC & FAGC
  • Xjyin Xiaochun Lu Shi Gaohua Chen
TD-SCDMA UE Chipset SyncDL Correlation
  • Xjyin Qian Lu Shi Gaohua Chen
TD-SCDMA UE Chipset EBIM
  • Zlfu Liyun Shengguo Hao Yun Zhang
TD-SCDMA UE Chipset HARQ(RM)
  • Zlfu Liyun Shengguo Hao Yun Zhang
TD-SCDMA UE Chipset DeEBIM
  • Yunyun Liyun Shengguo Hao Yun Zhang
TD-SCDMA UE Chipset DeHARQ(RM)
  • Yunyun Liyun Shengguo Hao Yun Zhang
TD-SCDMA UE Chipset CRC Top(Rx)
  • Yunyun Liyun Shengguo Hao Yun Zhang
TD-SCDMA UE Chipset CRC Top(Tx)
  • Zlfu Liyun Shengguo Hao Yun Zhang
TD-SCDMA UE Chipset RRC Rx Filter
  • Xjyin Qian Weifeng Peng Gaohua Chen
TD-SCDMA UE Chipset RRC Tx Filter
  • Xjyin Qian Weifeng Peng Gaohua Chen
TD-SCDMA UE Chipset Tx BIF
  • Xjyin Qian Weifeng Peng Gaohua Chen

Regular Team Meeting 2008/4/21

· Monday, April 21, 2008 ·

Attendees

Li Shuo, Chen Gaohua, Chen Chuntao, Peng Weifeng, Hao Shengguo, Zhang Yun, Zhao Xikai, Xia Bin

Topic

ASIC team regular meeting

Synopsis

Li Shuo
  • Finish gc200 FPGA testing last week
  • Start setup the platform for TD-SCDMA FPGA testing, including RDA RF interface design.
  • Chen Chuntao
  • Studying the TD channel estimation, for verification purpose.
  • Deliver a study summary on channel estimation upon understanding the algorithm spec in this week.
Chen Gaohua
  • Finish PMIC verification efforts.
  • Re-verify the RRC Tx filter upon the design changes. Close this effort in this week.
  • Start Tx BIF verification. Deliver test plan in this week.
  • Be assigned the efforts on RTL coding for JD Block V generation.
Peng Weifeng
  • Review the algorithm spec of DCC & DAGC module.
  • Deliver the micro-architecture spec of DCC & DAGC in this week.
Hao Shengguo
  • Investigate the TX BIM (bit-scrambling, 2nd interleaving, physical mapping) for supporting HSUPA
  • Deliver the micro-architecture of Tx BIM.
  • Be assigned the efforts on HARQ design, which supports both normal Rate-matching path and HSUPA path.
Zhang Yun
  • Await finalization of TX BIM for modifying testbench.
Zhao Xikai
  • Tavor-LE gate-level simulation.
  • Continue Tavor-LE gate-level simulation upon annotating the SDF of Mohawks IP.
  • Setup PMIC SOS server in Shanghai.
  • Review Chen Gaohua and Zhang Yun's SV testbench, and try to get them unified platform for TD datapath verification.
  • Review the Verilog Design Guilde.
Xia Bin
  • Sketch out the Verilog Design Guide.
  • Initiate the schedule and resource allocation for TD modem development.
  • Review Rx DCC & DAGC.
  • Consider the ASIC implementation of channel estimation.
  • Start micro-arch design of Block V Generation.
  • Start micro-arch design of Channel Estimation.
  • Deliver test plan for verifying Rx DCC & DAGC.
  • Review the Verilog Design Guilde.

Meeting Minutes 2008/4/18

· Saturday, April 19, 2008 ·

Attendees
  1. DSP Team: Zhu Shiyi, Yin Xiaojun
  2. Algorithm Team: Liu Shi, Zhou Liang, Zheng Ming
  3. ASIC Team: Zhao Xikai, Xia Bin, Peng Weifeng
Agenda
  1. Review Rx DCC & DAGC algorithm spec
  2. Review TD-SCDMA modem development schedule
Synopsis

1. Second round reviewing on DCC & DAGC algorithm spec, presented by Zheng Ming.
  • a. Issue-1: How to determine the historical DC value used in Alpha filter for calculating DC of current TS. This is an algorithm issue, and will not affect the HW implementation.
  • b. Issue-2: How to truncate the large bit width to small one in burst mode.
  • c. Reserve the 37-bit RSSI value uncutted, which will be reported to DSP.
  • d. Conclusion: the fixed-point algorithm is finalized by minor changes. ASIC person (Peng Weifeng) may start micro-arch design.
2. Discuss the IPs reusability for TD TxEnc path and RxDec path, which is silicon-proven in W-CDMA.
  • a. ASIC will re-design the Tx BIM (bit-scrambling, 2nd interleaving, physical mapping) to support HSUPA.
  • b. ASIC will design a new HARQ module for HSUPA, which also supports the nornal Rate Match path.
  • c. ASIC will reuse the CRC module used in W-CDMA, but need a CRC wrapper to fit the interface to DSP.
  • d. ASIC will reuse the Viterbi codec IP used in W-CDMA, so we are calling for the updated Viterbi design specification for understanding the design, which is must in the intergration stage and verfication stage.
  • e. ASIC will resue the Turbo codec IP used in W-CDMA, which has the same issue as Viterbi.
3. Review the TD modem development schedule, drafted by Xia Bin
  • a. The system definition and HW/SW partition are almost finished for most sub-modules.
  • b. The work flow will be going as: algorithm spec --> LLD iterations --> frozen algr spec --> micro-arch design --> RTL --> co-simulation.
  • c. Schedule for uplink sub-module design has been reviewed.
  • d. Schedule for downlink sub-module design is suspended at FFT engine, because the meeting is interrupted by another more urgent meeting.
  • e. We'll resume the schedule review meeting for the remaining sub-tasks in downlink path some day next week, mainly for ICS, ChEs, and Joint-detection.
Action Items
  1. Update the algorithm spec of DCC & DAGC upon the discussion today, and get it frozen. (Zheng Ming)
  2. Start micro-arch design on the module of DCC & Data-scaling. (Peng Weifeng)
  3. Start RTL verification of TX BIF sub-module. (Chen Gaohua, Peng Weifeng)
  4. Resume the TD schedule review meeting. (Zhu Shiyi, Liu Shi, Zhao Xikai, Xia Bin)
  5. Deliver Tx BIM system HLD spec including HSUPA path next week. (Zhu Shiyi)
  6. Review the spec of high-level timing scheduler and overall memory consumption, sketched by Zhu Shiyi. (DSP Team, Algr Team, ASIC Team)

Meeting Minutes 2008/4/9

· Wednesday, April 09, 2008 ·

Attendees
  • Liu Shi, Zhou Liang, Zheng Ming, Zhu Shiyi, Yin Xiaojun, Fu Zhiliang, Zhang Yunyun, Xia Bin, Peng Weifeng
Agenda
  • TD Channel Estimation & Joint Detection Review
Synopsis
  1. Zhou Liang gave a presentation on TD Channel Estimation in various working modes. We are almost arriving at the final algorithm spec. It is considered to add test mechanism for Channel Estimation.
  2. Discussed DCC & Data-scaling module before Channel Estimation. To get the ChEs result earlier, we designed a smart algorithm for DCC and Data-scaling on Rx data.
  3. Discussed the timing schedule for ChEs and JD between SW and HW, as well as among HW modules. The timing scheduler is very important to us, which will directly impact the performance of TD demodulator. This part must be taken double attention to. Zhu Shiyi has details in his documentation here \\sh2-wts01\TD L1 review.
Action Items
  1. Update the algorithm spec of Channel Estimation upon the discussion today. (Zhou Liang)
  2. Start micro-arch design on the module of DCC & Data-scaling. (Peng Weifeng)
  3. Evaluate the cost saving for Data-scaling from 14bit to 10bit. (Xia Bin)
  4. Make a decision on if we’ll cut the bits of Rx data based on the result of 3, and finalize the algorithm spec of DCC & Data-scaling module. (Liu Shi, Zheng Ming)
  5. Review the system documentation of implementation schedule. (Liu Shi, Xia Bin)
  6. Evaluate more accurate figures of Joint Detection. (Xia Bin)
  7. Start micro-arch design of Channel Estimation. (Xia Bin)