Weekly Report 2008/4/25

· Friday, April 25, 2008 · ,

Status update of TD-SCDMA
  1. Delivered micro-architectural design spec of JD Block-V Generation. (Xia Bin)
  2. Ongoing the iterative procedure on JD Matched Filter and Modify-module with algorithm designer. (Xia Bin)
  3. Delivered a guide for micro-arch documentation. (Xia Bin)
  4. Delivered micro-architectural design spec of Rx DCC & DAGC (Peng Weifeng)
  5. Ongoing testplan on Tx BIF. (Chen Gaohua)
  6. Delivered testbench overview of RRC Rx filter (Chen Gaohua)
  7. Ongoing the iterative procedure on Tx EBIM with L1 designers. (Hao Shengguo, Zhang Yun)
  8. Designing Tx EBIM micro-architecture (Hao Shengguo)
  9. Designing Tx EBIM testbench (Zhang Yun)
  10. Delivered testbench overview of FFT engine. (Zhang Yun)
  11. Reviewing the TDMA HLD draft spec (Shi Lu)
Plan for next week
  1. Have a review meeting on micro-arch design of DCC & DAGC. (ASIC Team)
  2. Have a review meeting on micro-arch design of JD Block-V Generation. (ASIC Team)
  3. Have a review meeting on HLD spec of TDMA engine with system group. (Shi Lu, Zhao Xikai, Xia Bin)
  4. Have a review meeting on Tx BIF testplan. (ASIC Team)
  5. Have a review meeting on Gaohua and Yun's verifcation platform. (ASIC Team)
  6. Start RTL design of Rx DCC & DAGC and complete the Alpha version. (Peng Weifeng)
  7. Deliver testplan documentation on Tx BIF for reviewing. (Chen Gaohua)
  8. Start RTL design of JD Block-V Generation if designer is available. (Chen Gaohua)
  9. Continue Tx EBIM micro-arch designing. (Hao Shengguo)
  10. Continue Tx EBIM testbench designing. (Zhang Yun)
  11. Go on micro-arch design of JD Channel Estimation and documentation. (Xia Bin)
  12. Go on iterative procedure on LLD of Joint Detection sub-modules with algr designers. (Xia Bin)
  13. Start iterative procedure on HLD of TDMA engine. (Shi Lu)