To-do List of TD Demodulation integration

1. Cholesky Decomposition is clear now. (done)
2. Fix timing violation of Matched Filter. Need to add a pipeline stage at the input data from Block-V and E0/E1 buffers. (done)
3. Fix timing violation of Correlation Matrix Gen. Need to add a pipeline stage at the input data from Block-V buffer, and also at the Block-V address generation. (done)
4. Replace the W-ROM of Channel Estimation with a fast process library. (done)
5. Add enable signal at latching point on multi-cycle path.

To-do List of TD Channel Estimation

1. Combine Mi and 1/Mi buffers (done)
2. Handle decimal dot position in overall data path (done)
3. Decimal dot alignment for data combination from S buffer and Alpha filter (done)
4. Noise power calculation in DwPTS mode (done)
5. Control path in Test mode (done)
6. Modify bit-width of Alpha, ThrhldGain, Weight to 12bits (done)
7. Timing closure in 208MHz (done)
8. Performance improvement
9. FFT overflow times for last stage

To-do List for Emergency

1. Done on 5/12/08
2. Done on 5/15/08

1. Re-evaluate the timing budget of Channel Estimation and Joint Detection.
   
2. Design Verilog template for TD modem RTL implementation, which is a unified solution for HW and ASPEC accessing a same SRAM bank by sharing a read/write port.