Milestone List for Next Week

· Friday, April 25, 2008 · ,

Following milestones would be achieved by the next weekend (Friday, May 2nd, 2008)
  • L1 System Phase
  1. HSUPA BIM/EBIM interface design spec (Fu Zhiliang)
  2. HSUPA HARQ(RM) interface design spec (Fu Zhiliang)
  3. Channel Estimation LLD design document (Zhu Shiyi, Xiao Dengwei)
  • Algorithm Phase
  1. None
  • ASIC Phase
  1. Finalize DCC & DAGC micro-arch design spec (Peng Weifeng)
  2. Kick off TDMA micro-arch design (Shi Lu)
  3. Deliver test plan document of Tx BIF and have it reviewed with ASIC Team (Chen Gaohua)