Meeting Minutes 2008/4/28

· Monday, April 28, 2008 ·

Attendees
  1. Zhao Xikai, Xia Bin, Peng Weifeng, Chen Gaohua, Zhu Shiyi, Yin Xiaojun, Xiao Dengwei, Liu Shi, Zheng Ming
Agenda
  1. DCC & DAGC micro-architectural design review
  2. JD Block-V Generation micro-architectural design review
Synopsis
  1. Midamble from RRC Filter stores in Rx MA buffer.
  2. Midamble from DCC & DAGC stores in FFT engine for immediately kick-off Channel Estimation.
  3. Add flags for MA buffer interface to indicate either original MA or DCCed MA.
  4. Apart from Channel Estimation, FFT engine should also be able to act as a standalone hardware accelerator for DSP.
  5. Add TDMA timestamps register for DSP read.
  6. Fix parameters Q=16, W=17 in JD Block-V Generation.
Action Items
  1. Update documentation of DCC & DAGC (Peng Weifeng)
  2. Update documentation of JD Block-V Generation (Xia Bin)
  3. Start DCC & DAGC RTL coding (Peng Weifeng)
  4. Start JD Block-V Generation RTL coding (Chen Gaohua)