Weekly Report 2008/4/30

Status update of TD-SCDMA

1. Review the micro-arch design of Rx DCC & DAGC. (ASIC Team)
   
2. Reviewed the micro-arch design of JD Block-V Generation. (ASIC Team)
   
3. Reviewed the SystemVerilog platform for module-level verification. (ASIC Team)
   
4. Reviewed the HLD specification of TDMA engine. (Xikai, Lu, Bin)
5. Ongoing Tx EBIM HLD iterative procedure and micro-arch design. (Shengguo, Yun)
6. Study HARQ spec. (Shengguo)
   
7. Ongoing JD Channel Estimation LLD iterative procedure. (Bin)
8. Ongoing JD Matched Filter/Correlation Matrix LLD iterative procedure. (Bin)
9. Re-evaluate the time consumption of JD path. (Bin)
   
10. Study SystemVerilog for verification. (Bin)
11. Ongoing TDMA HLD iterative procedure. (Lu)
12. Study Channel Estimation for verification. (Chuntao)
13. Designing testplan and testbench of Tx BIF for verification. (Gaohua)
14. Designing RTL of Rx DCC & DAGC. (Weifeng)
    

Plan for next week

1. Have a review meeting on Tx BIF testplan. (ASIC Team)
2. Start Tx BIF verification. (Gaohua)
3. Start Block-V Generation RTL design. (Gaohua)
   
4. Start micro-architectural design of TDMA engine. (Lu)
5. Start micro-architectural design of Channel Estimation. (Bin)
6. Start testplan and testbench design of DCC & DAGC. (Bin)
7. Continue JD LLD iterative procedure with algr designer. (Bin)
8. Re-evaluate the time consumption of JD path, especially for CYD/FS/BS. (Bin)
   
9. Start to design the Rx buffer (E1 / MA / E2). (Bin)
   
10. Continue studying Channel Estimation for verification. (Chuntao)
11. Finish DCC & DAGC RTL design and have it delivered. (Weifeng)
12. Continue Tx EBIM micro-architectural design. (Shengguo)
13. Continue Tx EBIM testbench design. (Yun)