Regular Team Meeting 2008/4/21

Attendees

Li Shuo, Chen Gaohua, Chen Chuntao, Peng Weifeng, Hao Shengguo, Zhang Yun, Zhao Xikai, Xia Bin

Topic

ASIC team regular meeting

Synopsis

Li Shuo

• Finish gc200 FPGA testing last week
• Start setup the platform for TD-SCDMA FPGA testing, including RDA RF interface design.
• Chen Chuntao
• Studying the TD channel estimation, for verification purpose.
• Deliver a study summary on channel estimation upon understanding the algorithm spec in this week.

Chen Gaohua

• Finish PMIC verification efforts.
• Re-verify the RRC Tx filter upon the design changes. Close this effort in this week.
• Start Tx BIF verification. Deliver test plan in this week.
• Be assigned the efforts on RTL coding for JD Block V generation.

Peng Weifeng

• Review the algorithm spec of DCC & DAGC module.
• Deliver the micro-architecture spec of DCC & DAGC in this week.

Hao Shengguo

• Investigate the TX BIM (bit-scrambling, 2nd interleaving, physical mapping) for supporting HSUPA
• Deliver the micro-architecture of Tx BIM.
• Be assigned the efforts on HARQ design, which supports both normal Rate-matching path and HSUPA path.

Zhang Yun

• Await finalization of TX BIM for modifying testbench.

Zhao Xikai

• Tavor-LE gate-level simulation.
• Continue Tavor-LE gate-level simulation upon annotating the SDF of Mohawks IP.
• Setup PMIC SOS server in Shanghai.
• Review Chen Gaohua and Zhang Yun's SV testbench, and try to get them unified platform for TD datapath verification.
• Review the Verilog Design Guilde.

Xia Bin

• Sketch out the Verilog Design Guide.
• Initiate the schedule and resource allocation for TD modem development.
• Review Rx DCC & DAGC.
• Consider the ASIC implementation of channel estimation.
• Start micro-arch design of Block V Generation.
• Start micro-arch design of Channel Estimation.
• Deliver test plan for verifying Rx DCC & DAGC.
• Review the Verilog Design Guilde.