Meeting Minutes 2008/4/18

Attendees

1. DSP Team: Zhu Shiyi, Yin Xiaojun
2. Algorithm Team: Liu Shi, Zhou Liang, Zheng Ming
3. ASIC Team: Zhao Xikai, Xia Bin, Peng Weifeng

Agenda

1. Review Rx DCC & DAGC algorithm spec
2. Review TD-SCDMA modem development schedule

Synopsis

1. Second round reviewing on DCC & DAGC algorithm spec, presented by Zheng Ming.

• a. Issue-1: How to determine the historical DC value used in Alpha filter for calculating DC of current TS. This is an algorithm issue, and will not affect the HW implementation.
• b. Issue-2: How to truncate the large bit width to small one in burst mode.
• c. Reserve the 37-bit RSSI value uncutted, which will be reported to DSP.
• d. Conclusion: the fixed-point algorithm is finalized by minor changes. ASIC person (Peng Weifeng) may start micro-arch design.

2. Discuss the IPs reusability for TD TxEnc path and RxDec path, which is silicon-proven in W-CDMA.

• a. ASIC will re-design the Tx BIM (bit-scrambling, 2nd interleaving, physical mapping) to support HSUPA.
• b. ASIC will design a new HARQ module for HSUPA, which also supports the nornal Rate Match path.
• c. ASIC will reuse the CRC module used in W-CDMA, but need a CRC wrapper to fit the interface to DSP.
• d. ASIC will reuse the Viterbi codec IP used in W-CDMA, so we are calling for the updated Viterbi design specification for understanding the design, which is must in the intergration stage and verfication stage.
• e. ASIC will resue the Turbo codec IP used in W-CDMA, which has the same issue as Viterbi.

3. Review the TD modem development schedule, drafted by Xia Bin

• a. The system definition and HW/SW partition are almost finished for most sub-modules.
• b. The work flow will be going as: algorithm spec --> LLD iterations --> frozen algr spec --> micro-arch design --> RTL --> co-simulation.
• c. Schedule for uplink sub-module design has been reviewed.
• d. Schedule for downlink sub-module design is suspended at FFT engine, because the meeting is interrupted by another more urgent meeting.
• e. We'll resume the schedule review meeting for the remaining sub-tasks in downlink path some day next week, mainly for ICS, ChEs, and Joint-detection.

Action Items

1. Update the algorithm spec of DCC & DAGC upon the discussion today, and get it frozen. (Zheng Ming)
2. Start micro-arch design on the module of DCC & Data-scaling. (Peng Weifeng)
3. Start RTL verification of TX BIF sub-module. (Chen Gaohua, Peng Weifeng)
4. Resume the TD schedule review meeting. (Zhu Shiyi, Liu Shi, Zhao Xikai, Xia Bin)
5. Deliver Tx BIM system HLD spec including HSUPA path next week. (Zhu Shiyi)
6. Review the spec of high-level timing scheduler and overall memory consumption, sketched by Zhu Shiyi. (DSP Team, Algr Team, ASIC Team)