Weekly Report 2008/5/31

· Saturday, May 31, 2008 · ,

Status update of Tavor-TD
  1. Delivered Channel Estimation micro-architectural design spec. (Bin)
  2. Review the JD matched filter LLD spec. (Bin)
  3. RTL code review on Rx DCC & DAGC and JD block-V gen. (Bin)
  4. Investigate the design detail of Turbo Codec IP and its test cases. (Shuo)
  5. Study algorithm of Turbo Codec. (Shuo)
  6. Passed all 7 testcase of Rx DCC & DAGC including direct test and random test. (Chuntao, Weifeng)
  7. Generated coverage report: Now the conditional coverage is 97.31% and toggle is 93.74%. Other 3 coverages are all 100%.(Chuntao)
  8. Start running the basic register test of Tx BIF module. (Weifeng)
  9. Debugging Tx EBIM and finished direct test. (Shengguo, Yun)
  10. Finished JD block-V generation verification including direct test and random test, as well as its verifiation coverage report. (Gaohua, Xikai)
  11. Get the comprehensive verification platform on Tx BIF done and start direct testcase development. (Gaohua)
  12. Debugging on ICS DLsync code correlation. (Lu)
  13. Setup the template on module-level verification platform, and setup the verification QA mechanism. (Xikai)
Next week's plan of Tavor-TD
  1. Have a joint review meeting with DSP group and Algr group on Channel Estimation micro-arch design. (Bin)
  2. Start Channel Estimation RTL coding. (Bin)
  3. Start JD match filter micro-arch design. (Bin)
  4. Focus on Turbo Decoder and try to figure out the reuse method of this IP. (Shuo)
  5. Help DSP team to setup the FPGA environment to accommodate the SPI driver development. (Shuo)
  6. Start Channel Estimation testplan and testbench design. (Chuntao)
  7. Continue on Rx DCC & DAGC coverage report analysis and get this module closed. (Chuntao, Weifeng)
  8. Continue on verification of Tx BIF. (Weifeng, Gaohua))
  9. Start Post-JD processing micro-architectural design. (Weifeng)
  10. Finish Tx EBIM random test. (Shengguo, Yun)
  11. Finish Tx RM/HARQ micro-arch design and deliver its design spec. (Shengguo)
  12. Add a minor change on JD block-V gen, and get it verified. (Gaohua)
  13. Continue work on ICS DLsync code correlation. (Lu)
  14. Start TDMA engine verifcation. (Xikai)