Weekly Report

Status update of Tavor-TD

1. Ongoing RTL coding of Channel Estimation. (Bin)
2. Delivered micro-architectural design spec of JD matched filter. (Bin)
3. RTL code review of JD blockv_gen. (Bin)
4. Completed Rx DCC & DAGC verification including code coverage report and analysis. (Chuntao, Weifeng)
5. Start studying Channel Estimation of verification. (Chuntao)
6. Ongoing verifying Tx BIF. (Gaohua, Weifeng)
7. Start studying post-JD processing module. (Weifeng)
8. Completed Tx E-BIM verification including code coverage report and analysis. (Yun, Shengguo)
9. Debug Turbo decoder's test cases and get more familiar with this design. (Shuo)
10. Dive into FIFO SPI module related issues. (Shuo)
11. Make design changes of ICS DLSync Code, especially fixing timing violations. (Lu)

Plan for next week

1. Continue RTL coding of Channel Estimation. (Bin)
2. Start RTL coding of JD matched filter after having it review with DSP and algr teams. (Bin)
3. RTL code review of Rx DCC & DAGC. (Bin)
4. Start to design testplan and testbench of Channel Estimation. (Chuntao)
5. Finish direct and random test cases of Tx BIF. (Gaohua, Weifeng)
6. Start post-JD micro-architectural design. (Weifeng)
7. Start studying HARQ/RM LLD spec for verification. (Yun)
8. Suport DSP team to develop TD transceiver SPI driver on Yarden platform. (Shuo)
9. Continue investigating Turbo decoder design. (Shuo)
10. Start study ICS Fast AGC LLD spec. (Lu)