Weekly Report 2008/5/24

· Sunday, May 25, 2008 · ,

Status update of Tavor-TD
  1. Channel Estimation micro-architectural design and documentation. This task is 80% finished. (Bin)
  2. Ongoing JD LLD iteration with algorithm engineer. (Bin)
  3. Ported simulation environment from modelsim to vcs. (Shuo)
  4. Turbo encoder simulation is ok, still debugging decoder.Need more knowledge about modem and turbo codec itself. (Shuo)
  5. Completed RTL coding of the EBIM and start debugging. (Shengguo)
  6. Write rough RM/HARQ spec. (Shengguo)
  7. EBIM verification plan and test plan review . (Yun)
  8. Write EBIM testbench and write basic reset/register test case. (Yun)
  9. Finished DCC & DAGC testbench design and start verification. (Chuntao)
  10. Debugging RTL of DCC & DAGC. (Weifeng)
  11. Finished RTL revision of Tx BIF. (Weifeng)
  12. Completed RTL coding of Block-V Generation, and start debugging. (Gaohua)
  13. Modified the Tx BIF testbench according to the revised RTL design and C-model. (Gaohua)
  14. Deliver the RTL code of TDMA engine. (Lu)
Plan for next week
  1. Deliver Channel Estimation micro-arch design spec, and get it reviewed. (Bin)
  2. Start JD matched filter micro-architectural design. (Bin)
  3. Study turbo codec algorithm (Shuo)
  4. Trace the design and gain more information about turbo codec. (Shuo)
  5. Continue debugging EBIM. (Shengguo)
  6. Detail HARQ/RM structure. (Shengguo)
  7. Verify EBIM with random test cases. (Yun)
  8. Continue verifying DCC & DAGC. (Chuntao)
  9. Continue debugging RTL of DCC & DAGC. (Weifeng)
  10. Debug the revised RTL of Tx BIF. (Weifeng)
  11. Debug RTL of Block-V generation. (Gaohua)
  12. Debug RTL of Tx BIF. (Gaohua)
  13. Start verifcation effort of TDMA engine. (Lu)