Weekly Report 5/17/08

· Saturday, May 17, 2008 · ,

Status update of TD
  1. Micro-architectural design of Channel Estimation. (Bin)
  2. Completed RTL design of Rx buffer. (Bin)
  3. Designed Verilog template for DSP and HW accessing SRAM/RF sharing one memory port. (Bin)
  4. Ongoing JD matched filter LLD iteration with algr engineer. (Bin)
  5. Discussed with Qian Li(algorithm team) about tx BIF module C model interface and have confirmed a draft version. (Gaohua)
  6. Investigated the timeslot format types in protocol file(3GPPTS25.221) and thought about the randomize generation in my testbench. (Gaohua)
  7. Discussed with Ming Zheng about the BlockV LLD and confirmed some concern problems(shift number, walsh code, and so on) (Gaohua)
  8. Released a version of the BlockV registers files(in attachment) and finished BlockV RTL coding for Q=16 mode(check in cvs, named blcokv_gen) (Gaohua)
  9. Finished RTL coding of DCC & DAGC. (Weifeng)
  10. Updated the Tx BIF design spec and revised RTL design. (Weifeng)
  11. Finish the EBIM spec with some feedback and detailed internal structure. (Shengguo)
  12. Modify the design, interface, sub-module spliting, and .etc. (Shengguo)
  13. Descuss EBIM C-model design for verification. (Yun)
  14. Write EBIM verification plan and test plan . (Yun)
  15. Write the random stimulus generator for TXBIM.
  16. Completed the DCC & DAGC testplan. (Chuntao)
  17. Designing DCC & DAGC testbench, get 70~80% done. (Chuntao)
  18. RTL design of TDMA engine. (Lu)
Plan for next week
  1. Continue Channel Estimation micro-arch design and deliver its draft spec. (Bin)
  2. Continue JD LLD iteration with algr engineer. (Bin)
  3. To implement the slot format type randomize generation in BIF testbench. (Gaohua)
  4. Finish block-V generation RTL code and deliver it for verification. (Gaohua)
  5. Start DCC & DAGC verification. (Weifeng, Chuntao)
  6. Start Tx BIF verification. (Weifeng, Gaohua)
  7. Finish EBIM RTL coding, and run simulation for basic test vector. (Shengguo)
  8. Deliver a initial RM spec as final LLD. (Shengguo)
  9. Deliver EBIM testplan for review. (Yun)
  10. Design EBIM testbench. (Yun)
  11. Finish TDMA RTL coding and deliver it for verification. (Lu)