Weekly Report 2008/5/9

· Friday, May 09, 2008 · ,

Status update of TD
  1. Modify Tx BIF module and update the design spec per System group's change. (Weifeng)
  2. RTL coding of Rx DCC & DAGC module. Hope to be delivered early next week. (Weifeng)
  3. Re-evaluated the JD path, particularly for timing budget in WF mode. (Bin)
  4. Discussing the CYD module for VLSI implementation issues with algr engineers. (Bin)
  5. RTL designing Rx buffer. (Bin)
  6. Micro-architectural design of Channel Estimation. (Bin)
  7. Finish discussion and chang about EBIM structure and modify the spec. (Shengguo)
  8. RTL coding of E-DCH mode interleaver. (Shengguo)
  9. Preparing the RM/HARQ micro-arch spec. (Shengguo)
  10. Read Tx BIM HLD spec and discuss issues with System engineer. (Yun)
  11. Writing C model requirement and deliver it to corresponding algr engineer. (Yun)
  12. Update the random stimulus generator for Tx BIM. (Yun)
  13. Be assigned the verification task of Rx DCC & DAGC module. (Chuntao)
  14. Getting familar with Channel Estimation. (Chuntao)
  15. Get Tx BIF testplan reviewed within ASIC Team. (Gaohua)
  16. Designing Tx BIF testbench. (Gaohua)
  17. Investigate the Block-V Generation module for RTL implementation. (Gaohua)
  18. Setup debug env. for 8206 EVB board. So far data receiving via 10bit interface seems OK. (Shuo)
Plan for next week
  1. Get the Rx DCC & DAGC RTL coding done, and start functional verification. (Weifeng)
  2. Get the modification of Tx BIF done for both RTL and documentation, and start functional verification. (Weifeng)
  3. Have a review meeting on demodulation path with System and Algr groups. (Bin, Xikai, Weifeng)
  4. Have a review meeting on TDMA microarchitectural design. (Lu, Bin, Xikai)
  5. Review the Verilog Design Guide. (ASIC Team)
  6. Micro-architectural design of Channel Estimation and its documentation. (Bin)
  7. Finish Rx buffer design. (Bin)
  8. Design Verilog template for memory access from both functional block and ASPEC bus. (Bin)
  9. Continue JD LLD iteration with algr guys. (Bin)
  10. Discuss architecture of EBIM for 2816/5ms data with System engineers. (Shengguo)
  11. Study HARQ hardware structure. (Shengguo)
  12. Discuss with algr engineer about Tx BIM C model. (Yun)
  13. EBIM testplan documentation. (Yun)
  14. Deliver testplan of DCC & DAGC. (Chuntao)
  15. Start testbench design of DCC & DAGC. (Chuntao)
  16. Deliver testbench of Tx BIF and start verification. (Gaohua)
  17. Start RTL coding of Block-V Generation. (Gaohua)
  18. Finish 10bit interface testing and transfer to System Team for SPI driver debug and tune. (Shuo)