To-do List of TD Channel Estimation

1. Combine Mi and 1/Mi buffers (done)
2. Handle decimal dot position in overall data path (done)
3. Decimal dot alignment for data combination from S buffer and Alpha filter (done)
4. Noise power calculation in DwPTS mode (done)
5. Control path in Test mode (done)
6. Modify bit-width of Alpha, ThrhldGain, Weight to 12bits (done)
7. Timing closure in 208MHz (done)
8. Performance improvement
9. FFT overflow times for last stage

Weekly Report

Status update of Tavor-TD

1. RTL coding of Channel Estimation, approximately 30% done. (Bin)
2. Generate code coverage and function coverage report for Tx E-BIM. (Yun)
3. Study RM-HARQ design spec and write verification plan. (Yun)
4. Studying spec of channel estimation and matched filter. And begin to prepare test plan and test bench for channel estimation. (Chuntao)
5. Verifying Tx BIF with direct cases and random cases. Basically the functional verfication is almost done. (Gaohua, Weifeng)
6. Studying the LLD doc of JD Post processing. (Weifeng)
7. RTL coding of RM/HARQ. (Shengguo)
8. Work together with DSP team to setup FPGA environment. Debugging dsp’s spi driver, not closed yet. Coding spi’s wrap, and debugging using FPGA. (Shuo)

Plan for next week

1. Continue Tavor-TD RTL design, and deliver the 1st version source code for verification. (Bin)
2. Write testbench for HARQ and wait for random input definition for parameter C-model. (Yun)
3. Write basic reset and register test case for HARQ. (Yun)
4. Start testplan and testbench design for Channel Estimation. (Chuntao)
5. Close the Tx BIF verification with code and functional coverage reports. (Gaohua Weifeng)
6. Contine JD post processing LLD iterative discussion with Algr engineer and start micro-arch design. (Weifeng)
7. Deliver the 1st version source of HARQ for verification. (Shengguo)
8. Close SPI related issue and back to support codec related issues. (Shuo)

Weekly Report

Status update of Tavor-TD

1. Ongoing RTL coding of Channel Estimation. (Bin)
2. Delivered micro-architectural design spec of JD matched filter. (Bin)
3. RTL code review of JD blockv_gen. (Bin)
4. Completed Rx DCC & DAGC verification including code coverage report and analysis. (Chuntao, Weifeng)
5. Start studying Channel Estimation of verification. (Chuntao)
6. Ongoing verifying Tx BIF. (Gaohua, Weifeng)
7. Start studying post-JD processing module. (Weifeng)
8. Completed Tx E-BIM verification including code coverage report and analysis. (Yun, Shengguo)
9. Debug Turbo decoder's test cases and get more familiar with this design. (Shuo)
10. Dive into FIFO SPI module related issues. (Shuo)
11. Make design changes of ICS DLSync Code, especially fixing timing violations. (Lu)

Plan for next week

1. Continue RTL coding of Channel Estimation. (Bin)
2. Start RTL coding of JD matched filter after having it review with DSP and algr teams. (Bin)
3. RTL code review of Rx DCC & DAGC. (Bin)
4. Start to design testplan and testbench of Channel Estimation. (Chuntao)
5. Finish direct and random test cases of Tx BIF. (Gaohua, Weifeng)
6. Start post-JD micro-architectural design. (Weifeng)
7. Start studying HARQ/RM LLD spec for verification. (Yun)
8. Suport DSP team to develop TD transceiver SPI driver on Yarden platform. (Shuo)
9. Continue investigating Turbo decoder design. (Shuo)
10. Start study ICS Fast AGC LLD spec. (Lu)

Weekly Report 2008/5/31

Status update of Tavor-TD

1. Delivered Channel Estimation micro-architectural design spec. (Bin)
2. Review the JD matched filter LLD spec. (Bin)
3. RTL code review on Rx DCC & DAGC and JD block-V gen. (Bin)
4. Investigate the design detail of Turbo Codec IP and its test cases. (Shuo)
5. Study algorithm of Turbo Codec. (Shuo)
6. Passed all 7 testcase of Rx DCC & DAGC including direct test and random test. (Chuntao, Weifeng)
7. Generated coverage report: Now the conditional coverage is 97.31% and toggle is 93.74%. Other 3 coverages are all 100%.(Chuntao)
8. Start running the basic register test of Tx BIF module. (Weifeng)
9. Debugging Tx EBIM and finished direct test. (Shengguo, Yun)
10. Finished JD block-V generation verification including direct test and random test, as well as its verifiation coverage report. (Gaohua, Xikai)
11. Get the comprehensive verification platform on Tx BIF done and start direct testcase development. (Gaohua)
12. Debugging on ICS DLsync code correlation. (Lu)
13. Setup the template on module-level verification platform, and setup the verification QA mechanism. (Xikai)

Next week's plan of Tavor-TD

1. Have a joint review meeting with DSP group and Algr group on Channel Estimation micro-arch design. (Bin)
2. Start Channel Estimation RTL coding. (Bin)
3. Start JD match filter micro-arch design. (Bin)
4. Focus on Turbo Decoder and try to figure out the reuse method of this IP. (Shuo)
5. Help DSP team to setup the FPGA environment to accommodate the SPI driver development. (Shuo)
6. Start Channel Estimation testplan and testbench design. (Chuntao)
7. Continue on Rx DCC & DAGC coverage report analysis and get this module closed. (Chuntao, Weifeng)
8. Continue on verification of Tx BIF. (Weifeng, Gaohua))
9. Start Post-JD processing micro-architectural design. (Weifeng)
10. Finish Tx EBIM random test. (Shengguo, Yun)
11. Finish Tx RM/HARQ micro-arch design and deliver its design spec. (Shengguo)
12. Add a minor change on JD block-V gen, and get it verified. (Gaohua)
13. Continue work on ICS DLsync code correlation. (Lu)
14. Start TDMA engine verifcation. (Xikai)

TD milestones for next week

Following milestones would be archieved by the next weekend (Friday, May 30, 2008)

L1 System Phase (Shiyi's team)

1. Complete HSDPA HLD documentation.
2. Complete Initial Cell Search Fast AGC LLD design.

Algorithm Phase (Stone's team)

1. Deliver fixed-point C code of JD matched filter.
   
2. Deliver fixed-point C code of HARQ.
   

ASIC Phase (Xikai's team)

1. Complete Block-V generation RTL coding.
   
2. Complete JD matched filter LLD iteration and joint review.
3. Complete HARQ LLD iteration and joint review.

Preacted or Delayed Items

1. Channel Estimation delayed 2 weeks at ASIC micro-architectural design stage.
   

Weekly Report 2008/5/24

Status update of Tavor-TD

1. Channel Estimation micro-architectural design and documentation. This task is 80% finished. (Bin)
2. Ongoing JD LLD iteration with algorithm engineer. (Bin)
3. Ported simulation environment from modelsim to vcs. (Shuo)
4. Turbo encoder simulation is ok, still debugging decoder.Need more knowledge about modem and turbo codec itself. (Shuo)
5. Completed RTL coding of the EBIM and start debugging. (Shengguo)
6. Write rough RM/HARQ spec. (Shengguo)
7. EBIM verification plan and test plan review . (Yun)
8. Write EBIM testbench and write basic reset/register test case. (Yun)
9. Finished DCC & DAGC testbench design and start verification. (Chuntao)
10. Debugging RTL of DCC & DAGC. (Weifeng)
11. Finished RTL revision of Tx BIF. (Weifeng)
12. Completed RTL coding of Block-V Generation, and start debugging. (Gaohua)
13. Modified the Tx BIF testbench according to the revised RTL design and C-model. (Gaohua)
14. Deliver the RTL code of TDMA engine. (Lu)

Plan for next week

1. Deliver Channel Estimation micro-arch design spec, and get it reviewed. (Bin)
2. Start JD matched filter micro-architectural design. (Bin)
3. Study turbo codec algorithm (Shuo)
4. Trace the design and gain more information about turbo codec. (Shuo)
5. Continue debugging EBIM. (Shengguo)
6. Detail HARQ/RM structure. (Shengguo)
7. Verify EBIM with random test cases. (Yun)
8. Continue verifying DCC & DAGC. (Chuntao)
9. Continue debugging RTL of DCC & DAGC. (Weifeng)
10. Debug the revised RTL of Tx BIF. (Weifeng)
11. Debug RTL of Block-V generation. (Gaohua)
12. Debug RTL of Tx BIF. (Gaohua)
13. Start verifcation effort of TDMA engine. (Lu)

TD milestones for next week

L1 System Phase (Shiyi's team)

1. Finish HARQ(RM) interface design and deliver HSUPA LLD spec.
2. Finish JD Matched Filter LLD design.

Algorithm Phase (Stone's team)

1. Deliver JD Matched Filter LLD spec.
2. Deliver HARQ LLD spec.

ASIC Phase (Xikai's team)

1. Deliver Channel Estimation micro-arch design spec.
2. Finish DCC & DAGC RTL verification.
3. Complete Block-V Gen testplan and testbench.
4. Finish EBIM RTL verifiction.
5. Finish interfacing with RF daughter card. (already done)