Weekly Report 2008/5/24

Status update of Tavor-TD

1. Channel Estimation micro-architectural design and documentation. This task is 80% finished. (Bin)
2. Ongoing JD LLD iteration with algorithm engineer. (Bin)
3. Ported simulation environment from modelsim to vcs. (Shuo)
4. Turbo encoder simulation is ok, still debugging decoder.Need more knowledge about modem and turbo codec itself. (Shuo)
5. Completed RTL coding of the EBIM and start debugging. (Shengguo)
6. Write rough RM/HARQ spec. (Shengguo)
7. EBIM verification plan and test plan review . (Yun)
8. Write EBIM testbench and write basic reset/register test case. (Yun)
9. Finished DCC & DAGC testbench design and start verification. (Chuntao)
10. Debugging RTL of DCC & DAGC. (Weifeng)
11. Finished RTL revision of Tx BIF. (Weifeng)
12. Completed RTL coding of Block-V Generation, and start debugging. (Gaohua)
13. Modified the Tx BIF testbench according to the revised RTL design and C-model. (Gaohua)
14. Deliver the RTL code of TDMA engine. (Lu)

Plan for next week

1. Deliver Channel Estimation micro-arch design spec, and get it reviewed. (Bin)
2. Start JD matched filter micro-architectural design. (Bin)
3. Study turbo codec algorithm (Shuo)
4. Trace the design and gain more information about turbo codec. (Shuo)
5. Continue debugging EBIM. (Shengguo)
6. Detail HARQ/RM structure. (Shengguo)
7. Verify EBIM with random test cases. (Yun)
8. Continue verifying DCC & DAGC. (Chuntao)
9. Continue debugging RTL of DCC & DAGC. (Weifeng)
10. Debug the revised RTL of Tx BIF. (Weifeng)
11. Debug RTL of Block-V generation. (Gaohua)
12. Debug RTL of Tx BIF. (Gaohua)
13. Start verifcation effort of TDMA engine. (Lu)

TD milestones for next week

L1 System Phase (Shiyi's team)

1. Finish HARQ(RM) interface design and deliver HSUPA LLD spec.
2. Finish JD Matched Filter LLD design.

Algorithm Phase (Stone's team)

1. Deliver JD Matched Filter LLD spec.
2. Deliver HARQ LLD spec.

ASIC Phase (Xikai's team)

1. Deliver Channel Estimation micro-arch design spec.
2. Finish DCC & DAGC RTL verification.
3. Complete Block-V Gen testplan and testbench.
4. Finish EBIM RTL verifiction.
5. Finish interfacing with RF daughter card. (already done)
   

Weekly Report 5/17/08

Status update of TD

1. Micro-architectural design of Channel Estimation. (Bin)
2. Completed RTL design of Rx buffer. (Bin)
3. Designed Verilog template for DSP and HW accessing SRAM/RF sharing one memory port. (Bin)
4. Ongoing JD matched filter LLD iteration with algr engineer. (Bin)
5. Discussed with Qian Li(algorithm team) about tx BIF module C model interface and have confirmed a draft version. (Gaohua)
6. Investigated the timeslot format types in protocol file(3GPPTS25.221) and thought about the randomize generation in my testbench. (Gaohua)
7. Discussed with Ming Zheng about the BlockV LLD and confirmed some concern problems(shift number, walsh code, and so on) (Gaohua)
8. Released a version of the BlockV registers files(in attachment) and finished BlockV RTL coding for Q=16 mode(check in cvs, named blcokv_gen) (Gaohua)
9. Finished RTL coding of DCC & DAGC. (Weifeng)
10. Updated the Tx BIF design spec and revised RTL design. (Weifeng)
11. Finish the EBIM spec with some feedback and detailed internal structure. (Shengguo)
12. Modify the design, interface, sub-module spliting, and .etc. (Shengguo)
13. Descuss EBIM C-model design for verification. (Yun)
14. Write EBIM verification plan and test plan . (Yun)
    
15. Write the random stimulus generator for TXBIM.
16. Completed the DCC & DAGC testplan. (Chuntao)
17. Designing DCC & DAGC testbench, get 70~80% done. (Chuntao)
18. RTL design of TDMA engine. (Lu)
    

Plan for next week

1. Continue Channel Estimation micro-arch design and deliver its draft spec. (Bin)
2. Continue JD LLD iteration with algr engineer. (Bin)
3. To implement the slot format type randomize generation in BIF testbench. (Gaohua)
4. Finish block-V generation RTL code and deliver it for verification. (Gaohua)
5. Start DCC & DAGC verification. (Weifeng, Chuntao)
6. Start Tx BIF verification. (Weifeng, Gaohua)
7. Finish EBIM RTL coding, and run simulation for basic test vector. (Shengguo)
8. Deliver a initial RM spec as final LLD. (Shengguo)
9. Deliver EBIM testplan for review. (Yun)
10. Design EBIM testbench. (Yun)
11. Finish TDMA RTL coding and deliver it for verification. (Lu)

Milestone List for Next Week

Following milestones would be achieved by the next weekend (Friday, May 16th, 2008)

• L1 System Phase (Shiyi's Team)
  

1. Finish IR buffer/HARQ HSDPA HLD design.
   

• Algorithm Phase (Stone's Team)

1. Finish C coding of Channel Estimation.
2. Deliver Block-V Generation LLD spec.
3. Deliver EBIM LLD spec.
   

• ASIC Phase (Xikai's Team)

1. Deliver micro-architectural design spec of Channel Estimation.
2. Finish DCC & DAGC RTL coding.
3. Deliver DCC & DAGC testplan for review.
4. Finish DCC & DAGC testbench design for verification.
   

Weekly Report 2008/5/9

Status update of TD

1. Modify Tx BIF module and update the design spec per System group's change. (Weifeng)
2. RTL coding of Rx DCC & DAGC module. Hope to be delivered early next week. (Weifeng)
3. Re-evaluated the JD path, particularly for timing budget in WF mode. (Bin)
4. Discussing the CYD module for VLSI implementation issues with algr engineers. (Bin)
5. RTL designing Rx buffer. (Bin)
6. Micro-architectural design of Channel Estimation. (Bin)
7. Finish discussion and chang about EBIM structure and modify the spec. (Shengguo)
   
8. RTL coding of E-DCH mode interleaver. (Shengguo)
9. Preparing the RM/HARQ micro-arch spec. (Shengguo)
10. Read Tx BIM HLD spec and discuss issues with System engineer. (Yun)
11. Writing C model requirement and deliver it to corresponding algr engineer. (Yun)
12. Update the random stimulus generator for Tx BIM. (Yun)
13. Be assigned the verification task of Rx DCC & DAGC module. (Chuntao)
14. Getting familar with Channel Estimation. (Chuntao)
15. Get Tx BIF testplan reviewed within ASIC Team. (Gaohua)
16. Designing Tx BIF testbench. (Gaohua)
17. Investigate the Block-V Generation module for RTL implementation. (Gaohua)
18. Setup debug env. for 8206 EVB board. So far data receiving via 10bit interface seems OK. (Shuo)
    

Plan for next week

1. Get the Rx DCC & DAGC RTL coding done, and start functional verification. (Weifeng)
2. Get the modification of Tx BIF done for both RTL and documentation, and start functional verification. (Weifeng)
3. Have a review meeting on demodulation path with System and Algr groups. (Bin, Xikai, Weifeng)
4. Have a review meeting on TDMA microarchitectural design. (Lu, Bin, Xikai)
5. Review the Verilog Design Guide. (ASIC Team)
6. Micro-architectural design of Channel Estimation and its documentation. (Bin)
7. Finish Rx buffer design. (Bin)
8. Design Verilog template for memory access from both functional block and ASPEC bus. (Bin)
9. Continue JD LLD iteration with algr guys. (Bin)
10. Discuss architecture of EBIM for 2816/5ms data with System engineers. (Shengguo)
11. Study HARQ hardware structure. (Shengguo)
12. Discuss with algr engineer about Tx BIM C model. (Yun)
    
13. EBIM testplan documentation. (Yun)
14. Deliver testplan of DCC & DAGC. (Chuntao)
15. Start testbench design of DCC & DAGC. (Chuntao)
    
16. Deliver testbench of Tx BIF and start verification. (Gaohua)
    
17. Start RTL coding of Block-V Generation. (Gaohua)
18. Finish 10bit interface testing and transfer to System Team for SPI driver debug and tune. (Shuo)
    

To-do List for Emergency

1. Done on 5/12/08
2. Done on 5/15/08

1. Re-evaluate the timing budget of Channel Estimation and Joint Detection.
   
2. Design Verilog template for TD modem RTL implementation, which is a unified solution for HW and ASPEC accessing a same SRAM bank by sharing a read/write port.

My Deliverables This Week

1. JD Channel Estimation Micro-architectural spec.
2. Timing budget of ChEs and JD.
3. DCC & DAGC testplan and testbench.
4. Rx Buffer RTL design.